1. Field of the Invention
This invention relates to a method for programming, reading and erasing a memory, and more particularly, to a method for programming, reading and erasing a flash memory.
2. Description of Related Art
A non-volatile memory is a data storage device that allows the data stored thereon to be modified and erased, and the data reside on the memory with or without supplied power. The non-volatile memory, including the flash memory developed by Intel, uses a floating gate of a metal-oxide-semiconductor (MOS) transistor within each of the memory cells to store a bit of binary data, a `0` or a `1`. The MOS transistor normally consists of physical components including source/drain regions, a floating gate, a control gate and a tunneling oxide layer.
The method for storing a bit of binary data to a non-volatile memory or erasing a bit of binary data from a non-volatile memory is based on the tunneling effect caused by hot electrons, excited electrons. While a bit of binary data is written to a memory cell, a positive voltage is applied on the drain region as the source region is normally grounded. In addition, another positive voltage is applied on the control gate to force the hot electrons, flowing to ward the drain region from the source region, to pass the tunneling oxide layer and to be injected into the floating gate. Once the hot electrons get in the floating gate, they are trapped by the high energy-barrier material surrounding the floating gate, and reside therein. Since the hot electrons pass through a portion the tunneling oxide layer next to the drain region, the forgoing method is also named as drain side injection (DSI) method.
While the stored binary data is a subject to be erased, the trapped hot electrons are forced to flow outward the floating gate and pass through the tunneling oxide layer by applying a positive voltage on the source region and a negative voltage on the control gate.
A conventional flash memory is illustrated in FIGS. 1 through 4, wherein FIG. 1 shows the layout conventional flash memory, FIG. 2 shows its schematic circuit diagram and FIGS. 3 and 4 show the structural cross-sectional views of the conventional flash memory viewed from different view points, the I--I plane and the II--II plane.
As shown in FIG. 3, a cross-sectional view of plane I--I showing the structure of a conventional flash memory shown in FIG. 1, a transistor consists of source/drain regions 101 and 102, a tunneling oxide layer, a floating gate 105 and a control gate 107.
Referring to FIG. 3 together with FIGS. 2 and 4, A P-type substrate 100 and a N-type source region 101 are both grounded through a wire SL. A N-type drain region 102 is connected to a positive voltage source of about 6 to 8 volts through a contact 109 and a bit line 110, that is, BL1 or BL2 shown in FIG. 2. The control gate 107 is connected to a positive voltage source of about 12 to 16 volts through a word line WL1, WL2, or WL3 shown in FIG. 2. Because of the voltage potential difference between the source region 101 and the drain region 102, hot electrons are then flow from the source region 101 toward the drain region 102 through a N-channel 103. Among the hot electrons flowing toward the drain region, some of them are collected and guided to the ground by the drain region 102. Most hot electrons pass through the tunneling oxide layer 104 and are injected into the floating gate 105 by the attraction of the electric field generated the positive voltage applied on the control gate 107. Once the hot electrons get in the floating gate 105, they are trapped by the high energy-barrier material, oxide 104, dielectric 106 and 108, surrounding the floating gate 105, and reside therein. Once a certain number of hot electrons are trapped within the floating gate, which means a bit of binary data is written to the memory. The required current for the foregoing programming process is about 500 .mu.A.
While the binary data stored in a memory cell is a subject to be read, a positive voltage of about 5 volts is applied on the control gate 107 through the word line, WL1, WL2 or WL3 in FIG. 2. A positive voltage of about 1.5 volts is applied on the drain region 102 through the bit line BL1 or BL2. The substrate 100 and the source region 101 are still grounded by the source line SL. If there are trapped electrons within the floating gate 105, there are no electrons are flowing form the source region 101 toward the drain region 102. Therefore, a pre-defined `1` or `0` is read. Otherwise, a pre-defined `0` or `1` is read if there are no electrons trapped inside the floating gate 105. The foregoing reading process obtains a current signal of about 70 .mu.A while the floating gate 105 contains trapped electrons.
For erasing a bit of binary data stored in a memory cell of a flash memory, a negative voltage of about 10 to 15 volts in amplitude is applied on the control gate 107 through the word line WL1, WL2 or WL3. A positive voltage of about 5 volts is applied on the drain region 102. The substrate 100 and the source region 101 are still grounded. The voltage difference between the substrate and the control gate generates an electric field that forces the electrons trapped within the floating gate 105 to pass through the tunneling oxide layer 104, and flow toward the drain region.
Since the conventional DSI method for programming a flash memory requires a pretty high voltage in order to have a sufficient current, The high voltage tends toward degrading the reliability of the flash memory.
The current signal, which is about 70 .mu.A, obtained by using the foregoing reading method is too low, so that the reading efficiency is limited.
In addition, the foregoing erasing process does not only force the trapped electrons to flow out of the floating gate, the process sometimes excessively drains electrons from the floating gate to cause over-erasing. The over-erasing effect further causes the change on the threshold voltage of the N-channel that leads to a erroneous reading in the follow-up reading process.